Semiconductor substrate thickness variation within a single substrate can present problems when a die is attached in a flip chip configuration to the substrate. Too much variation of thickness can result in not all interconnects being coupled to the substrate, resulting in reduced overall product yield. Thickness variation may present even greater challenges when a die is a larger size die such as a server processor die since there is a larger area of the substrate where the die will be attached. The larger area means that the substrate needs a larger area of thickness uniformity in order to have all interconnects couple to the substrate. Thickness variation of a substrate may be decreased by reducing individual thickness variation of dielectric layers and metal routing layers in the substrate. However, package electrical performance requirements, such as I/O routing, power, and impedance, may constrain this approach to reducing substrate thickness variation. For example, a power delivery layer design may have a higher copper density in the design to minimize DC resistance, thereby presenting a challenge of balancing power delivery with substrate thickness variation.